Links:
- OpenRISC

开板板简介

管脚定义

下面数据来源于DE0_Nano_User_Manual.pdf的Chapter 3-3.5 Expansion headers.

GPIO-0 Pin Assignments

Signal Name	FPGA Pin No.	Descritption	I/O Standard
GPIO_0_IN0	PIN_A8	GPIO Connection DATA	3.3V
GPIO_00	PIN_D3	GPIO Connection DATA	3.3V
GPIO_0_IN1	PIN_B8	GPIO Connection DATA	3.3V
GPIO_01	PIN_C3	GPIO Connection DATA	3.3V
GPIO_02	PIN_A2	GPIO Connection DATA	3.3V
GPIO_03	PIN_A3	GPIO Connection DATA	3.3V
GPIO_04	PIN_B3	GPIO Connection DATA	3.3V
GPIO_05	PIN_B4	GPIO Connection DATA	3.3V
GPIO_06	PIN_A4	GPIO Connection DATA	3.3V
GPIO_07	PIN_B5	GPIO Connection DATA	3.3V
GPIO_08	PIN_A5	GPIO Connection DATA	3.3V
GPIO_09	PIN_D5	GPIO Connection DATA	3.3V
GPIO_010	PIN_B6	GPIO Connection DATA	3.3V
GPIO_011	PIN_A6	GPIO Connection DATA	3.3V
GPIO_012	PIN_B7	GPIO Connection DATA	3.3V
GPIO_013	PIN_D6	GPIO Connection DATA	3.3V
GPIO_014	PIN_A7	GPIO Connection DATA	3.3V
GPIO_015	PIN_C6	GPIO Connection DATA	3.3V
GPIO_016	PIN_C8	GPIO Connection DATA	3.3V
GPIO_017	PIN_E6	GPIO Connection DATA	3.3V
GPIO_018	PIN_E7	GPIO Connection DATA	3.3V
GPIO_019	PIN_D8	GPIO Connection DATA	3.3V
GPIO_020	PIN_E8	GPIO Connection DATA	3.3V
GPIO_021	PIN_F8	GPIO Connection DATA	3.3V
GPIO_022	PIN_F9	GPIO Connection DATA	3.3V
GPIO_023	PIN_E9	GPIO Connection DATA	3.3V
GPIO_024	PIN_C9	GPIO Connection DATA	3.3V
GPIO_025	PIN_D9	GPIO Connection DATA	3.3V
GPIO_026	PIN_E11	GPIO Connection DATA	3.3V
GPIO_027	PIN_E10	GPIO Connection DATA	3.3V
GPIO_028	PIN_C11	GPIO Connection DATA	3.3V
GPIO_029	PIN_B11	GPIO Connection DATA	3.3V
GPIO_030	PIN_A12	GPIO Connection DATA	3.3V
GPIO_031	PIN_D11	GPIO Connection DATA	3.3V
GPIO_032	PIN_D12	GPIO Connection DATA	3.3V
GPIO_033	PIN_B12	GPIO Connection DATA	3.3V

GPIO-1 Pin Assignments

Signal Name	FPGA Pin No.	Descritption	I/O Standard
GPIO_1_IN0	PIN_T9	GPIO Connection DATA	3.3V
GPIO_10	PIN_F13	GPIO Connection DATA	3.3V
GPIO_1_IN1	PIN_R9	GPIO Connection DATA	3.3V
GPIO_11	PIN_T15	GPIO Connection DATA	3.3V
GPIO_12	PIN_T14	GPIO Connection DATA	3.3V
GPIO_13	PIN_T13	GPIO Connection DATA	3.3V
GPIO_14	PIN_R13	GPIO Connection DATA	3.3V
GPIO_15	PIN_T12	GPIO Connection DATA	3.3V
GPIO_16	PIN_R12	GPIO Connection DATA	3.3V
GPIO_17	PIN_T11	GPIO Connection DATA	3.3V
GPIO_18	PIN_T10	GPIO Connection DATA	3.3V
GPIO_19	PIN_R11	GPIO Connection DATA	3.3V
GPIO_110	PIN_P11	GPIO Connection DATA	3.3V
GPIO_111	PIN_R10	GPIO Connection DATA	3.3V
GPIO_112	PIN_N12	GPIO Connection DATA	3.3V
GPIO_113	PIN_P9	GPIO Connection DATA	3.3V
GPIO_114	PIN_N9	GPIO Connection DATA	3.3V
GPIO_115	PIN_N11	GPIO Connection DATA	3.3V
GPIO_116	PIN_L16	GPIO Connection DATA	3.3V
GPIO_117	PIN_K16	GPIO Connection DATA	3.3V
GPIO_118	PIN_R16	GPIO Connection DATA	3.3V
GPIO_119	PIN_L15	GPIO Connection DATA	3.3V
GPIO_120	PIN_P15	GPIO Connection DATA	3.3V
GPIO_121	PIN_P16	GPIO Connection DATA	3.3V
GPIO_122	PIN_R14	GPIO Connection DATA	3.3V
GPIO_123	PIN_N16	GPIO Connection DATA	3.3V
GPIO_124	PIN_N15	GPIO Connection DATA	3.3V
GPIO_125	PIN_P14	GPIO Connection DATA	3.3V
GPIO_126	PIN_L14	GPIO Connection DATA	3.3V
GPIO_127	PIN_N14	GPIO Connection DATA	3.3V
GPIO_128	PIN_M10	GPIO Connection DATA	3.3V
GPIO_129	PIN_L13	GPIO Connection DATA	3.3V
GPIO_130	PIN_J16	GPIO Connection DATA	3.3V
GPIO_131	PIN_K15	GPIO Connection DATA	3.3V
GPIO_132	PIN_J13	GPIO Connection DATA	3.3V
GPIO_133	PIN_J14	GPIO Connection DATA	3.3V

Table 3-8 Pin Assignments for 2x13 Header

Signal Name	FPGA Pin No.	Descritption	I/O Standard
GPIO_2[0]	PIN_A14	GPIO Connection DATA[0]	3.3V
GPIO_2[1]	PIN_B16	GPIO Connection DATA[1]	3.3V
GPIO_2[2]	PIN_C14	GPIO Connection DATA[2]	3.3V
GPIO_2[3]	PIN_C16	GPIO Connection DATA[3]	3.3V
GPIO_2[4]	PIN_C15	GPIO Connection DATA[4]	3.3V
GPIO_2[5]	PIN_D16	GPIO Connection DATA[5]	3.3V
GPIO_2[6]	PIN_D15	GPIO Connection DATA[6]	3.3V
GPIO_2[7]	PIN_D14	GPIO Connection DATA[7]	3.3V
GPIO_2[8]	PIN_F15	GPIO Connection DATA[8]	3.3V
GPIO_2[9]	PIN_F16	GPIO Connection DATA[9]	3.3V
GPIO_2[10]	PIN_F14	GPIO Connection DATA[10]	3.3V
GPIO_2[11]	PIN_G16	GPIO Connection DATA[11]	3.3V
GPIO_2[12]	PIN_G15	GPIO Connection DATA[12]	3.3V
GPIO_2_IN[0]	PIN_E15	GPIO Input	3.3V
GPIO_2_IN[1]	PIN_E16	GPIO Input	3.3V
GPIO_2_IN[2]	PIN_M16	GPIO Input	3.3V

Table 3-9 Pin Assignments for ADC

Signal Name	FPGA Pin No.	Descritption	I/O Standard
ADC_CS_N	PIN_A10	Chip select	3.3V
ADC_SADDR	PIN_B10	Digital data input	3.3V
ADC_SDAT	PIN_A9	Digital data output	3.3V
ADC_SCLK	PIN_B14	Digital clock input	3.3V

JTAG

OpenRisc

GCC工具链

or1k-toolchain-build

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~$ git clone https://github.com/stffrdhrn/or1k-toolchain-build
~$ cd or1k-toolchain-build
~$ docker build -t or1k-toolchain-build or1k-toolchain-build/

设置挂载目录变量,运行容器编译.如果build-gcc.sh内的资源链接失效了,需要找一个替代修改它,如：QEMU_URL=https://github.com/vamanea/qemu-or32/archive/v2.0.2.tar.gz.

# The location where you have tarballs, so they dont need to be
# downloaded every time you build
CACHEDIR=/home/user/work/docker/volumes/src
# The location where you want your output to go
OUTPUTDIR=/home/user/work/docker/volumes/crosstool

docker run -it --rm \
  -e MUSL_ENABLED=1 \
  -e NEWLIB_ENABLED=1 \
  -e NOLIB_ENABLED=1 \
  -e GCC_VERSION=9.0.1 \
  -e BINUTILS_VERSION=2.32.51 \
  -e LINUX_HEADERS_VERSION=4.19.1 \
  -e MUSL_VERSION=1.1.20 \
  -e GMP_VERSION=6.1.2 \
  -v ${OUTPUTDIR}:/opt/crosstool:Z \
  -v ${CACHEDIR}:/opt/crossbuild/cache:Z \
    or1k-toolchain-build

编译成功后,如下：

ls
or1k-elf-9.0.1-20210204.tar.xz
or1k-elf-gcc-9.0.1-20210204.log.gz
or1k-elf-gcc-9.0.1-20210204.sum
or1k-elf-gxx-9.0.1-20210204.log.gz
or1k-elf-gxx-9.0.1-20210204.sum
or1k-linux-9.0.1-20210204.tar.xz
or1k-linux-musl-9.0.1-20210204.tar.xz
or1k-linux-musl-gcc-9.0.1-20210203.log.gz
or1k-linux-musl-gcc-9.0.1-20210203.sum
or1k-linux-musl-gcc-9.0.1-20210204.log.gz
or1k-linux-musl-gcc-9.0.1-20210204.sum
or1k-linux-musl-gxx-9.0.1-20210203.log.gz
or1k-linux-musl-gxx-9.0.1-20210203.sum
or1k-linux-musl-gxx-9.0.1-20210204.log.gz
or1k-linux-musl-gxx-9.0.1-20210204.sum
relnotes-9.0.1-20210204.md

这里把or1k-linux-9.0.1-20210204.tar.xz解压安装到本地,并设置相应的环境变量如下：

export ALTERA_PATH="/home/michael/3TB-DISK/intelFPGA_lite/20.1/"
export PATH=$PATH:$ALTERA_PATH/quartus/bin

export ARCH=openrisc
export CROSS_COMPILE=or1k-linux-
export PATH=$PATH:`pwd`/toolchain-rootfs/or1k-linux/bin

或者单独编译or1k-gcc

~$ git clone https://github.com/openrisc/or1k-gcc
~$ cd or1k-gcc/
~$ mkdir build-linux
~$ cd build-linux && ../configure && make -j4
~$ make install DESTPATH=<absolute  path>

编译`ORPSOC`

~$ git clone https://github.com/mczerski/orpsoc-de0_nano
~$ export ALTERA_PATH="/home/fullpath/QuartusIIWebEdition13.0.0.156/quartus"
~$ export PATH=$PATH:$ALTERA_PATH/bin
~$ make OR32_TOOL_PREFIX=or1k-linux- all

编译Linux

~$ tar xvf linux-4.16.14.tar.xz
~$ cd linux-4.16.14
~$ wget -c https://kevinmehall.net/openrisc/guide/de0_nano.dts.txt -O arch/openrisc/boot/dts/de0_nano.dts

~$ make ARCH=openrisc CROSS_COMPILE="or1k-linux-" or1ksim_defconfig
/** Select Processor type and Features -> Builtin DTB and type de0_nano */
~$ make ARCH=openrisc CROSS_COMPILE="or1k-linux-" menuconfig
~$ make ARCH=openrisc CROSS_COMPILE="or1k-linux-"

烧写入bitstream

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~$ cd orpsoc/boards/altera/de0_nano/syn/quartus/run
~$ make OR32_TOOL_PREFIX=or1k-linux- all
~$ make pgm

连接串号

根据上面GPIO的管脚定义,以及下面的信息,连接正确的rx,tx.

cat boards/altera/de0_nano/syn/quartus/tcl/UART0_pin_assignments.tcl
set_location_assignment PIN_D8 -to uart0_srx_pad_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_srx_pad_i
set_location_assignment PIN_F8 -to uart0_stx_pad_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_stx_pad_o

FuseSOC 试用

安装fuseSoc


~$ git clone https://github.com/olofk/fusesoc

~$ cd fusesoc && pip install -e .

OR
~$ pip install fusesoc

安装fusesoc 库

从网络安装.

1	~$ fusesoc library add intgen https://github.com/openrisc/intgen.git

从本地安装

~$ git clone https://github.com/openrisc/mor1kx-generic.git
~$ git clone https://github.com/openrisc/or1k_marocchino.git

~$ fusesoc library add mor1kx-generic `pwd`/mor1kx-generic
~$ fusesoc library add or1k_marocchino `pwd`/or1k_marocchino

~$ fusesoc list-cores
Available cores:

Core                      Cache status  Description
================================================================================
::blinky:0               :      local : <No description>
::intgen:0               :      local : Interrupt Generator For testing Processors
::mor1kx-generic:1.1     :      local : Minimal mor1kx simulation environment
::or1k_marocchino:5.0-r3 :      local : <No description>
::plights:0              :      local : <No description>
::rv_sopc:0              :      local : RISC V system on programmable chip example
::wb_intercon_gen_ng:0   :      local : CAPI=2 .core file description based Wishbone Interconnect generator

查看fusesoc.conf配置.

~$ cat fusesoc.conf
[library.mor1kx-generic]
location = /fullpath/FPGA-DE0-Nano/openrisc/mor1kx-generic
sync-uri = /fullpath/FPGA-DE0-Nano/openrisc/mor1kx-generic
sync-type = local
auto-sync = true

[library.or1k_marocchino]
location = /fullpath/FPGA-DE0-Nano/openrisc/or1k_marocchino
sync-uri = /fullpath/FPGA-DE0-Nano/openrisc/or1k_marocchino
sync-type = local
auto-sync = true

[library.intgen]
location = /fullpath/FPGA-DE0-Nano/openrisc/intgen
sync-uri = /fullpath/FPGA-DE0-Nano/openrisc/intgen
sync-type = local
auto-sync = true

[library.fusesoc-demos]
location = fusesoc_libraries/fusesoc-demos
sync-uri = https://github.com/Oxore/fusesoc-demos
sync-type = git
auto-sync = true

Fusesoc-demos

1	fusesoc library add https://github.com/Oxore/fusesoc-demos

RISC-V

links:
- linux-on-litex-vexriscv
- VexRiscv

安装`Quartus20`

这里只是安装QuartusLiteSetup-20.1.1.720-linux.run再加两个设备文件,没下载整个安装tar包,总包体积在6.5GB左右.

litex-boards测试编译

这里使用litex-hub里的项目测试,Quartus安装到~/intelFPGA_lite/20.1/quartus目录下.注意,加上--load参数项,必须先运行jtagd服务,否则quartus_pgm无法进行jtag烧写.

~$ export PATH=~/riscv64-toolchain/bin:~/intelFPGA_lite/20.1/quartus/bin:$PATH
~$ jtagd --foreground --debug
~$ cd litex-boards/litex_boards
~$ targets/terasic_de0nano.py --uart-name=jtag_uart --build --load

其实最终的编译脚本是如下内容.

linux-on-litex-vexriscv$ cat build/de0nano/gateware/build_de0nano.sh
# Autogenerated by LiteX / git: 55a79030
quartus_map --read_settings_files=on  --write_settings_files=off de0nano -c de0nano
quartus_fit --read_settings_files=off --write_settings_files=off de0nano -c de0nano
quartus_asm --read_settings_files=off --write_settings_files=off de0nano -c de0nano
quartus_sta de0nano -c de0nano
if [ -f "de0nano.sof" ]
then
    quartus_cpf -c de0nano.sof de0nano.rbf
fi

linux-on-litex-vexriscv编译测试

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~$ cd linux-on-litex-vexriscv
~$ export PATH=~/riscv64-toolchain/bin:~/intelFPGA_lite/20.1/quartus/bin:$PATH
~$ ./make.py --board=de0nano --build --load

运行--load参数时,需要确保jtagd是运行的,这里如下面所示,最终是使用quartus_pgm -m jtag -c USB-Blaster加载的.

[...]
Info: Command: quartus_pgm -m jtag -c USB-Blaster -o p;/home/michael/workspace-xilinx/RISC-V/litex-hub/litex/linux-on-litex-vexriscv/build/de0nano/gateware/de0nano.sof@1
Info (213046): Using programming cable "USB-Blaster on 127.0.0.1 [3-3]"
Info (213011): Using programming file /home/michael/workspace-xilinx/RISC-V/litex-hub/litex/linux-on-litex-vexriscv/build/de0nano/gateware/de0nano.sof with checksum 0x0085AEAF for device EP4CE22F17@1
Info (209060): Started Programmer operation at Sat Feb 26 11:35:48 2022
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x020F30DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Sat Feb 26 11:35:49 2022
Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 315 megabytes
    Info: Processing ended: Sat Feb 26 11:35:49 2022
    Info: Elapsed time: 00:00:32
    Info: Total CPU time (on all processors): 00:00:00

通过`JTAG-UART`查看启动信息

这里脚本默认是选择serial进行通信的,上面我在编译时选择了--uart-name=jtag_uart,想测试使用板的上USB JTAG的方式来进行uart通信.

~$ ./targets/terasic_de0nano.py --help
 [...]
 --no-uart
          Disable UART. (default: False)
  --uart-name UART_NAME
          UART type/name. (default: serial)
  --uart-baudrate UART_BAUDRATE
          UART baudrate. (default: 115200)
  --uart-fifo-depth UART_FIFO_DEPTH
          UART FIFO depth. (default: 16)
[...]

新建一个openocd的配置文件,针对de0nano EP4CE22F17的参数设置,如下:

litex_boards$ cat prog/openocd_de0nano.cfg
adapter driver usb_blaster
usb_blaster lowlevel_driver ftdi
set _CHIPNAME EP4CE22F17
set FPGA_TAPID 0x020F30DD
adapter speed 6000
jtag newtap $_CHIPNAME tap -irlen 10 -expected-id $FPGA_TAPID
#scan_chain
gdb_port disabled
tcl_port disabled

连接如下

 ~/.local/bin/litex_term jtag --jtag-config=./prog/openocd_de0nano.cfg
port is 20000
got ir value 2
Open On-Chip Debugger 0.11.0+dev-00562-g5ab74bde0-dirty (2022-02-07-19:44)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
jtagstream_serve
Info : usb blaster interface using libftdi
Info : This adapter doesn't support configurable speed
Info : JTAG tap: EP4CE22F17.tap tap/device found: 0x020f30dd (mfg: 0x06e (Altera), part: 0x20f3, ver: 0x0)
Warn : gdb services need one or more targets defined

连接到jtag-uart就直接挂住了,没有出来串口终端, 而通过litex_term连接jtag的参数是包装了openocd的命令行,等价与如下命令：

1	~$ openocd -f ./prog/openocd_de0nano.cfg -f stream.cfg -c <....>

因为--build完成后会在当前目录下生成stream.cfg文件,它就是用TCL脚本定义的openocd的配置文件,它的自动生成来源是位于:litex/litex/build/openocd.py里, 片段如下：

litex$ tail -n 20 litex/litex/build/openocd.py
}

proc jtagstream_serve {tap port} {
    set sock [socket stream.server $port]
    $sock readable [list jtagstream_client $tap $sock]
    stdin readable [list jtagstream_exit $sock]
    vwait forever
    $sock close
}
"""
        write_to_file("stream.cfg", cfg)
        print("port is {:d}".format(port))
        print("got ir value {:d}".format(self.get_ir(chain,config)))
        script = "; ".join([
            "init",
            "irscan $_CHIPNAME.tap {:d}".format(self.get_ir(chain, config)),
            "jtagstream_serve $_CHIPNAME.tap {:d}".format(port),
            "exit",
        ])
        self.call(["openocd", "-f", config, "-f", "stream.cfg", "-c", script])

想通过板上的USB接口,连接jtag_uart的方式不成功.

通过串口查看系统启动信息

因为使用jtag_uart方式连接串口不成功,还是选择默认的serial方式连接,因为板上没有USB to UART的功能,看相关文档也没说明如何连接到板上的uart,通过搜索源码发现如下的定义:

litex-boards$ cat litex_boards/platforms/terasic_de0nano.py
[...]
 # Switches
    ("sw", 0, Pins("M1"),  IOStandard("3.3-V LVTTL")),
    ("sw", 1, Pins("T8"),  IOStandard("3.3-V LVTTL")),
    ("sw", 2, Pins("B9"),  IOStandard("3.3-V LVTTL")),
    ("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")),

    # Serial
    ("serial", 0,
        # Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
        # GND on JP1 Pin 12.
        Subsignal("tx", Pins("JP1:10"), IOStandard("3.3-V LVTTL")),
        Subsignal("rx", Pins("JP1:8"),  IOStandard("3.3-V LVTTL"))
    ),

    # SDR SDRAM
    ("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")),
[...]

这里使用FTDI 2232H连接如下：

DE0-nano JP1                FT2232H
GPIO_05 Pin8     <------->  AD0 TXD
GPIO_07 Pin10    <------->  AD1 RXD
GND     Pin12    <------->  GND

到这里就可以使用litex_term或者minicom来连接板上串口了,如果出现乱码,就是UART baudrate问题,这里是默认其实是1Mbps(1e6),而且发现在某宝买的很多USB to UART在连接1Mbps还是会出现乱码,不能输入等问题,我换成FTDI 2232H就可以正常使用了.

litex-boards $ minicom -o -b 1000000 -D /dev/ttyUSB0

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS CRC passed (1f65f3e6)

 Migen git sha1: ac70301
 LiteX git sha1: 7cc781f7

--=============== SoC ==================--
CPU:            VexRiscv SMP-LINUX @ 50MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            64KiB
SRAM:           8KiB
L2:             2KiB
SDRAM:          32768KiB 16-bit @ 50MT/s (CL-2 CWL-2)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 15.8MiB/s
   Read speed: 11.7MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
             Timeout
No boot medium found

--============= Console ================--

litex>

可以通过help查看可以支持的命令

litex> help
LiteX BIOS, available commands:

help                     - Print this help
ident                    - Identifier of the system
crc                      - Compute CRC32 of a part of the address space
flush_cpu_dcache         - Flush CPU data cache
flush_l2_cache           - Flush L2 cache
leds                     - Set Leds value

boot                     - Boot from Memory
reboot                   - Reboot
serialboot               - Boot from Serial (SFL)

mem_list                 - List available memory regions
mem_read                 - Read address space
mem_write                - Write address space
mem_copy                 - Copy address space
mem_test                 - Test memory access
mem_speed                - Test memory speed
mem_cmp                  - Compare memory content

sdram_test               - Test SDRAM


litex> ident

Ident: LiteX SoC on DE0-Nano

leds命令可以控制板上的led0~led7的开关,

litex> leds 255  # 全部亮灯

Settings Leds to 0xff
litex> leds 1    # led0 亮

Settings Leds to 0x1

litex>  leds 11  # led0,led1,led3亮, (1 << 0) + (1 << 1) + (1 << 3)

Settings Leds to 0xb

添加`SPI-SDCard`外设

de0-nano板子上没有接sdcard的插槽,这里给它在JP1 Headers上连接一个SPI-SDCard插槽,并且让它能从SDCard boot方式,加载Linux.所以需修改相应的源码,先是在linux-on-litex-vexriscv/make.py里的De0Nano类下面的参数soc_capabilities添加spisdcard,如下：

litex-hub/linux-on-litex-vexriscv$ cat make.py
[...]
class De0Nano(Board):
    soc_kwargs = {"l2_size" : 2048} # Use Wishbone and L2 for memory accesses.
    def __init__(self):
        from litex_boards.targets import de0nano
        Board.__init__(self, de0nano.BaseSoC, soc_capabilities={
            # Communication
            "serial",
            "spisdcard"
        }, bitstream_ext=".sof")
[...]

再去到litex-hub/litex-boards的项目下,添加如下补丁修改

litex-hub/litex-boards$ git diff litex_boards/platforms/terasic_de0nano.py
diff --git a/litex_boards/platforms/terasic_de0nano.py b/litex_boards/platforms/terasic_de0nano.py
index 3284ddc..7a810f7 100644
--- a/litex_boards/platforms/terasic_de0nano.py
+++ b/litex_boards/platforms/terasic_de0nano.py
@@ -115,6 +115,14 @@ _io = [
         "F15 F16 F14 G16 G15"),
         IOStandard("3.3-V LVTTL")
     ),
+    # SDCard
+    ("spisdcard", 0,
+        Subsignal("clk",  Pins("JP1:18")),
+        Subsignal("cs_n", Pins("JP1:20")),
+        Subsignal("mosi", Pins("JP1:14"), Misc("WEAK_PULL_UP_RESISTOR ON")),
+        Subsignal("miso", Pins("JP1:16"), Misc("WEAK_PULL_UP_RESISTOR ON")),
+        IOStandard("3.3-V LVTTL")
+    ),
 ]

 # Connectors ---------------------------------------------------------------------------------------

编译linux-on-litex-vexriscv

1	linux-on-litex-vexriscv$ ./make.py --board=de0nano --build

完成后,先把一张SD卡格式成用fdisk修改分区类型为W95 FAT32,再用mkfs.fat格化它.再把linux-on-litex-vexriscv/images里面的文件复到SD卡的根目录里.SPI-SDCard模块与JP1接线如下：

SPI-Card Module              de0-nano JP1  FPGA Pin No
    CS         <---------->    JP1:20      GPIO_015 C6
    CLK        <---------->    JP1:18      GPIO_013 D6
    SDO        <---------->    JP1:16      GPIO_011 A6
    SDI        <---------->    JP1:14      GPIO_09  D5
    GND        <---------->    GND
    3V3        <---------->    3V3

上面的接线可以参考litex_boards/platforms/terasic_de0nano.py里的代码与上面介绍里GPIO-0 Pin Assignments的描述去理解与开发.

1	linux-on-litex-vexriscv$ ./make.py --board=de0nano --load

串口连接,并从SDCard booting

linux-on-litex-vexriscv$ minicom -o -b 1000000 -D /dev/ttyUSB0

(c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS CRC passed (1038d38c)

 Migen git sha1: ac70301
 LiteX git sha1: 7f49c523

--=============== SoC ==================--
CPU:            VexRiscv SMP-LINUX @ 50MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            64KiB
SRAM:           8KiB
L2:             2KiB
SDRAM:          32768KiB 16-bit @ 50MT/s (CL-2 CWL-2)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 16.7MiB/s
   Read speed: 20.3MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
             Timeout
Booting from SDCard in SPI-Mode...
Booting from boot.json...
Copying Image to 0x40000000 (7531468 bytes)...
[########################################]
Copying rv32.dtb to 0x40ef0000 (2621 bytes)...
[########################################]
Copying rootfs.cpio to 0x41000000 (3786240 bytes)...
[########################################]
Copying opensbi.bin to 0x40f00000 (53640 bytes)...
[########################################]
Executing booted program at 0x40f00000
[...]

如果从SDCard启动失败,先确保卡的分区格式是W95 FAT32,再换一张卡测试一下,因为我这边使用一张512MB的旧卡,另一张是1GB的旧卡,都无法检测到,换了一张32GB,128GB卡,都能成功加载运行.好像enjoy-digital/litesdcard对旧卡兼容有问题,或者是其它未知的原因.

quartus_cpf命令

查看参数帮助说明,如：

~$ quartus_cpf --help=rpd

Topic: rpd

To generate a Raw Programming Data File (.rpd), specify the input
file name and output file name. Make sure the file extension
of the output file is .rpd. The input file can be only a
Programmer Object File (.pof).

---------
Examples:
---------

# To convert .pof to .rpd
quartus_cpf -c <input_pof_file> <output_rpd_file>

# To use a Conversion Setup File (.cof) created with
# the Convert Programming Files dialog box in the UI
quartus_cpf -c <input_cof_file>

查看sof文件的信息

~$ quartus_cpf --info de0nano.sof
                File: de0nano.sof
            File CRC: 0x24F3
             Creator: Quartus Prime Compiler Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
             Comment: Untitled
              Device: EP4CE22F17
       Data checksum: 0x008595BA
       JTAG usercode: 0x008595BA
        Project Hash: 0x

生成svf文件

1	~$ quartus_cpf -c -q 6.0MHz -g 3.3 -n p de0nano.sof de0nano.svf

生成rpd文件

1 2	~$ quartus_cpf -c -d EPCS64 de0nano.sof de0nano.pof ~$ quartus_cpf -c -d EPCS64 -s EP4CE22F17 de0nano.pof de0nano.rpd

生成jic文件,可以使用Quartus Prime IDE -> Tools -> Programmer -> Add File...进行烧写,需确保jtagd服务是运行的.
1
~$ quartus_cpf -c -d EPCS64 -s EP4CE22F17 de0nano.sof de0nano.jic

用`openocd`加载`svf`文件.

根据板子参数，创建一个openocd的连接配置文件.

~$ cat > openocd_de0nano.cfg <<EOF
adapter driver usb_blaster
usb_blaster lowlevel_driver ftdi
set CHIPNAME EP4CE22F17
set FPGA_TAPID 0x020F30DD # 通过jtagconfig取得
adapter speed 6000
jtag newtap $CHIPNAME tap -irlen 10 -expected-id $FPGA_TAPID
init
scan_chain

EOF

加载到FPGA.

~$ openocd -f ./openocd_de0nano.cfg -c "svf  de0nano.svf progress" -c exit
Open On-Chip Debugger 0.11.0+dev-00562-g5ab74bde0-dirty (2022-02-07-19:44)
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
Info : usb blaster interface using libftdi
Info : This adapter doesn't support configurable speed
Info : JTAG tap: EP4CE22F17.tap tap/device found: 0x020f30dd (mfg: 0x06e (Altera), part: 0x20f3, ver: 0x0)
Warn : gdb services need one or more targets defined
   TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-- ------------------- -------- ---------- ---------- ----- ----- ------
 0 EP4CE22F17.tap         Y     0x020f30dd 0x020f30dd    10 0x01  0x03

svf processing file: "de0nano.svf"
  0%  FREQUENCY 1.20E+07 HZ;
Error: Translation from khz to adapter speed not implemented

  0%  TRST ABSENT;
  0%  ENDDR IDLE;
  0%  ENDIR IRPAUSE;
  0%  STATE IDLE;
  0%  SIR 10 TDI (002);
  0%  RUNTEST IDLE 12000 TCK ENDSTATE IDLE;
 95%  	FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);
 95%  SIR 10 TDI (004);
 95%  RUNTEST 60 TCK;
 95%  	000000000000000000000000000000000000000000000000000000000000000000);
 95%  SIR 10 TDI (003);
 95%  RUNTEST 49152 TCK;
 95%  RUNTEST 512 TCK;
 95%  SIR 10 TDI (3FF);
 95%  RUNTEST 12000 TCK;
 95%  STATE IDLE;

Time used: 0m1s439ms
svf file programmed successfully for 17 commands with 0 errors

烧写到`SPI FLASH`

openFPGALoader Intel/Altera
这里使用openFPGALoader -b de0nano -f de0nano.rpd显示烧写错误:flash stackflow,后面使用下面的命令就可以正常烧写到Flash.

1	~$ openFPGALoader -c usb-blaster --fpga-part ep4ce2217 -f de0nano.rbf

UrJtag使用

直接使用apt-get install urjtag的版本较老,是不支持ep4c22,显示如下：

~$ jtag
jtag> cable UsbBlaster vid=0x09fb pid=0x6001 interface=0
Connected to libftdi driver.
jtag> detect
IR length: 10
Chain length: 1
Device Id: 00000010000011110011000011011101 (0x020F30DD)
  Manufacturer: Altera (0x0DD)
  Unknown part! (0010000011110011) (/usr/share/urjtag/altera/PARTS)

通过参照这里,从最新(urjtag-2021.03)源码去编译它,这里还需要去FTDI的官网去下载D2XX Drivers
下载D2XX Drivers

~$ wget -c https://ftdichip.com/wp-content/uploads/2021/09/libftd2xx-x86_64-1.4.24.tgz
~$ tar xvf libftd2xx-x86_64-1.4.24.tgz
release/
release/release-notes.txt
release/WinTypes.h
[...]

编译安装urjtag-2021.03

~$ wget -c https://sourceforge.net/projects/urjtag/files/urjtag/2021.03/urjtag-2021.03.tar.xz/download
~$ tar xvf urjtag-2021.03.tar.xz
~$ cd urjtag-2021.03
~4 CLFAGS=-I$PWD/../release LDFLAGS="-L$PWD/../release/build -lftd2xx" ./configure --with-libusb  --with-libftdi  --with-ftd2xx
[...]
  Libraries:
    libusb     : 1.0
    libftdi    : yes (have async mode)
    libftd2xx  : yes
    inpout32   : no

  Subsystems:
    SVF        : yes
    BSDL       : yes
    STAPL      : no

  Drivers:
    Bus        : ahbjtag arm9tdmi au1500 avr32 bcm1250 blackfin bscoach ejtag ejtag_dma fjmem ixp425 ixp435 ixp465 jopcyc h7202 lh7a400 mpc5200 mpc824x mpc8313 mpc837x ppc405ep ppc440gx_ebc8 prototype pxa2x0 pxa27x s3c4510 sa1110 sh7727 sh7750r sh7751r sharc_21065L sharc_21369_ezkit slsup3 tx4925 zefant_xs3
    Cable      : arcom byteblaster dirtyjtag dlc5 ea253 ei012 ft2232 gpio ice100 igloo jlink keithkoep lattice mpcbdm triton usbblaster vsllink wiggler xpc
    Lowlevel   : direct ftdi ftd2xx ppdev

  Language bindings:
    python     : yes
~$ make && make install

应用ep4ce22描述文件的补丁

~$ cd /usr/local/share/urjtag$
~$ sudo patch -p1 < ~/urjtag-descriptors.patch
patching file altera/ep4ce22/ep4ce22
patching file altera/ep4ce22/STEPPINGS
patching file altera/PARTS
Hunk #1 succeeded at 28 (offset 2 lines).
michael@debian:/usr/local/share/urjtag$ /usr/local/bin/jtag

补丁文件

~$ cat urjtag-descriptors.patch
diff -Naur urjtag-orig/altera/ep4ce22/ep4ce22 urjtag/altera/ep4ce22/ep4ce22
--- urjtag-orig/altera/ep4ce22/ep4ce22	1970-01-01 10:00:00.000000000 +1000
+++ urjtag/altera/ep4ce22/ep4ce22	2014-07-30 21:48:09.652857260 +1000
@@ -0,0 +1,12 @@
+instruction length 10
+register DIR 32
+register USERCODE 32
+register BSR 732
+register BYPASS 1
+instruction HIGHZ 0000001011 BYPASS
+instruction CLAMP 0000001010 BYPASS
+instruction USERCODE 0000000111 USERCODE
+instruction IDCODE 0000000110 DIR
+instruction SAMPLE/PRELOAD 0000000101 BSR
+instruction EXTEST 0000001111 BSR
+instruction BYPASS 1111111111 BYPASS
diff -Naur urjtag-orig/altera/ep4ce22/STEPPINGS urjtag/altera/ep4ce22/STEPPINGS
--- urjtag-orig/altera/ep4ce22/STEPPINGS	1970-01-01 10:00:00.000000000 +1000
+++ urjtag/altera/ep4ce22/STEPPINGS	2014-07-30 21:48:09.644857260 +1000
@@ -0,0 +1,23 @@
+#
+# $Id: STEPPINGS 897 2007-12-29 13:02:32Z arniml $
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# as published by the Free Software Foundation; either version 2
+# of the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+# 02111-1307, USA.
+#
+# Written by H Hartley Sweeten <hsweeten@visionengravers.com>
+#
+
+# bits 31-28 of the Device Identification Register
+0000	ep4ce22		0
diff -Naur urjtag-orig/altera/PARTS urjtag/altera/PARTS
--- urjtag-orig/altera/PARTS	2014-07-28 22:19:56.968449502 +1000
+++ urjtag/altera/PARTS	2014-07-30 21:48:08.464857263 +1000
@@ -26,3 +26,4 @@
 0111000100101000	epm7128aetc100		EPM7128AETC100
 0111000001100100	epm3064a		EPM3064A
 0010000010110010	ep2c8			EP2C8
+0010000011110011	ep4ce22			EP4CE22

运行新版UrJtag

~$ /usr/local/bin/jtag

UrJTAG 2021.03 #
Copyright (C) 2002, 2003 ETC s.r.o.
Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors

UrJTAG is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
There is absolutely no warranty for UrJTAG.

warning: UrJTAG may damage your hardware!
Type "quit" to exit, "help" for help.

jtag> cable UsbBlaster vid=0x09fb pid=0x6001 interface=0
Connected to libftdi driver.
jtag> detect
IR length: 10
Chain length: 1
Device Id: 00000010000011110011000011011101 (0x020F30DD)
  Manufacturer: Altera (0x0DD)
  Part(0):      EP4CE22 (0x20F3)
  Stepping:     0
  Filename:     /usr/local/share/urjtag/altera/ep4ce22/ep4ce22
jtag> cable usbblaster driver=ftdi
Connected to libftdi driver.
jtag> detect
IR length: 10
Chain length: 1
Device Id: 00000010000011110011000011011101 (0x020F30DD)
  Manufacturer: Altera (0x0DD)
  Part(0):      EP4CE22 (0x20F3)
  Stepping:     0
  Filename:     /usr/local/share/urjtag/altera/ep4ce22/ep4ce22
jtag> print chain
 No. Manufacturer              Part                 Stepping Instruction          Register
-------------------------------------------------------------------------------------------------------------------
*  0 Altera                    EP4CE22              0        BYPASS               BYPASS

其它项目

open-design/riscv-soc-cores
ikwzm/FPGA-SoC-Linux, 下一步实践.
fpgarduino需要实践一下.
olofk/serv SERV - the SErial RISC-V CPU by olofk
Dmitriy0111/nanoFOX
openFPGALoader通用烧写工具
Extracting firmware from devices using JTAG

`USB Blaster`连接问题

Altera Design Software
因为这里只想使用quartus_pgm命令,就只下载了QuartusProgrammerSetup-16.1.0.196-linux.run.

~$ jtagd --foreground --debug

~$ ./jtagd --user-start --foreground
~$ ./jtagconfig
Error (Server error) when scanning hardware

测看系统日志

~$ dmesg
[...]
[25811.819181] usb 4-2: USB disconnect, device number 16
[25814.375520] usb 4-2: new full-speed USB device number 17 using xhci_hcd
[25814.550270] usb 4-2: New USB device found, idVendor=09fb, idProduct=6001, bcdDevice= 4.00
[25814.550283] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[25814.550289] usb 4-2: Product: USB-Blaster
[25814.550293] usb 4-2: Manufacturer: Altera
[25814.550297] usb 4-2: SerialNumber: 91d28408

直接运行jtagconfig命令,就出现下面这个错.

1 2	~$ ./jtagconfig Error when scanning hardware - Server error

然后用strace运行只过滤查看network运行情况如下：

~$ strace -e trace=network jtagconfig
[...]
si_stime=0} ---
socket(AF_INET, SOCK_STREAM, IPPROTO_IP) = 3
setsockopt(3, SOL_TCP, TCP_NODELAY, [1], 4) = 0
setsockopt(3, SOL_SOCKET, SO_LINGER, {l_onoff=1, l_linger=10}, 8) = 0
connect(3, {sa_family=AF_INET, sin_port=htons(1309), sin_addr=inet_addr("127.0.0.1")}, 16) = -1 EINPROGRESS (Operation now in progress)
socket(AF_INET, SOCK_STREAM, IPPROTO_IP) = 4
setsockopt(4, SOL_TCP, TCP_NODELAY, [1], 4) = 0
setsockopt(4, SOL_SOCKET, SO_LINGER, {l_onoff=1, l_linger=10}, 8) = 0
connect(4, {sa_family=AF_INET, sin_port=htons(1309), sin_addr=inet_addr("127.0.0.1")}, 16) = -1 EINPROGRESS (Operation now in progress)
getsockopt(3, SOL_SOCKET, SO_ERROR, [0], [4]) = 0
recvfrom(3, "", 2, 0, NULL, NULL)       = 0
getsockopt(4, SOL_SOCKET, SO_ERROR, [0], [4]) = 0
recvfrom(4, "", 2, 0, NULL, NULL)       = 0
recvfrom(-1, 0x1e4ca0c, 2, 0, NULL, NULL) = -1 EBADF (Bad file descriptor)

为排除硬件问题,又没有第二台电脑系统可试.使用Virtualbox安装了一个同版本的系统测试,发现在虚拟机里不做任何设置,就可以正常发现设备.如下:
1
2
3
4
~$ ./jtagconfig
1) USB-Blaster [2-2]
Unable to read device chain - JTAG chain broken
再次按装官方文档,安装添加udev相关设置,再把jtagd开启调试模式如下：

~# cat>/etc/udev/rules.d/51-altera-usb-blaster.rules<<EOF
SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6001", MODE="0666"
SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6002", MODE="0666"
SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6003", MODE="0666"
SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6010", MODE="0666"
SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6810", MODE="0666"
EOF

~$ jtagd --foreground --debug
JTAG daemon started
Using config file /etc/jtagd/jtagd.conf
Remote JTAG permitted when password set
USB-Blaster "USB-Blaster" firmware version 4.00
USB-Blaster endpoints out=02(64), in=81(64); urb size=1024
USB-Blaster added "USB-Blaster [4-2]"
USB-Blaster port (/dev/bus/usb/004/017) opened

但是直接运行jtagconfig还是会报Error when scanning hardware - Server error错误.后面按照上述文档进行下面的设置就可以了.

`jtagd`服务端配置

~# cp /fullpath/intelFPGA_lite/16.1/qprogrammer/linux64/pgm_parts.txt /etc/jtagd/jtagd.pgm_parts
~# echo "Password = \"123456\";" > /etc/jtagd/jtagd.conf
~# killall -9 jtagd
~$ jtagd --foreground --debug
JTAG daemon started
Using config file /etc/jtagd/jtagd.conf
Remote JTAG permitted when password set
USB-Blaster "USB-Blaster" firmware version 4.00
USB-Blaster endpoints out=02(64), in=81(64); urb size=1024
USB-Blaster added "USB-Blaster [6-2]"
USB-Blaster port (/dev/bus/usb/006/002) opened
USB-Blaster "USB-Blaster" firmware version 4.00
USB-Blaster endpoints out=02(64), in=81(64); urb size=1024
USB-Blaster reports JTAG protocol version 0, using version 0

`jtagconfig`配置

~$ jtagconfig --addserver 127.0.0.1 123456
~$ jtagconfig
1) USB-Blaster on 127.0.0.1 [6-2]
  020F30DD   EP3C25/EP4CE22

谢谢支持

微信二维码:

Sunrise 博客

玩转FPGA_DE0-Nano

开板板简介

管脚定义

GPIO-0 Pin Assignments

GPIO-1 Pin Assignments

Table 3-8 Pin Assignments for 2x13 Header

Table 3-9 Pin Assignments for ADC

JTAG

OpenRisc

GCC工具链

编译`ORPSOC`

编译Linux

烧写入bitstream

连接串号

FuseSOC 试用

安装fuseSoc

安装fusesoc 库

Fusesoc-demos

RISC-V

安装`Quartus20`

litex-boards测试编译

linux-on-litex-vexriscv编译测试

通过`JTAG-UART`查看启动信息

通过串口查看系统启动信息

添加`SPI-SDCard`外设

quartus_cpf命令

用`openocd`加载`svf`文件.

烧写到`SPI FLASH`

UrJtag使用

其它项目

`USB Blaster`连接问题

`jtagd`服务端配置

`jtagconfig`配置

谢谢支持

开板板简介

管脚定义

GPIO-0 Pin Assignments

GPIO-1 Pin Assignments

Table 3-8 Pin Assignments for 2x13 Header

Table 3-9 Pin Assignments for ADC

JTAG

OpenRisc

GCC工具链

编译ORPSOC

编译Linux

烧写入bitstream

连接串号

FuseSOC 试用

安装fuseSoc

安装fusesoc 库

Fusesoc-demos

RISC-V

安装Quartus20

litex-boards测试编译

linux-on-litex-vexriscv编译测试

通过JTAG-UART查看启动信息

通过串口查看系统启动信息

添加SPI-SDCard外设

quartus_cpf命令

用openocd加载svf文件.

烧写到SPI FLASH

UrJtag使用

其它项目

USB Blaster连接问题

jtagd服务端配置

jtagconfig配置

谢谢支持

编译`ORPSOC`

安装`Quartus20`

通过`JTAG-UART`查看启动信息

添加`SPI-SDCard`外设

用`openocd`加载`svf`文件.

烧写到`SPI FLASH`

`USB Blaster`连接问题

`jtagd`服务端配置

`jtagconfig`配置